Dr. Joungho Kim, Professor
Dept. of Electrical Engineering, Korea Advanced Institute of Science and Technology
Recently, we are facing a newly emerging technology and industrial transition, named as 4th Industrial Revolution, which is based big data platforms, deep learning algorithms, and high performance GPU computing machines. Accordingly, demands for terabyte/s bandwidth GPU-DRAM computing performance are rapidly increasing. However, continuously growing gaps between GPU performance and DRAM data bandwidth are becoming the critical drawbacks. In order to meet the required terabyte/s bandwidth needs for the big data platforms, deep learning algorithms, we are proposing novel 2.5D/3D High Bandwidth Memory (HBM) solution using TSV and Si interposer technologies.
In this presentation, we will introduce the basic approaches and designs of terabyte/s bandwidth 2.5D/3D HBM (High-bandwidth Memory Module), in particular, which will be useful for deep learning artificial intelligent servers. Especially, we will talk about the signal and power integrity design, simulation methods, analysis results of TSV and Si interposer channels, including GPU-DRAM channels, and high-speed serial channels. In addition, we will discuss PDN impedance, and decoupling capacitor schemes as well. Finally, we will propose next generation 2.5D/3D HBM designs using active interposer and equalization schemes to even increase the bandwidths with lower power consumptions. .
Dr. Joungho Kim received B.S. and M.S. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 1984 and 1986, respectively, and Ph.D degree in electrical engineering from the University of Michigan, Ann Arbor, in 1993. In 1994, he joined Memory Division of Samsung Electronics, where he was engaged in Gbit-scale DRAM design. In 1996, he moved to KAIST (Korea Advanced Institute of Science and Technology). He is currently professor at electrical engineering department of KAIST. Since joining KAIST, his research centers on EMC modeling, design, and measurement methodologies of 3D IC, TSV, Interposer, System-in-Package, multi-layer PCB, and wireless power transfer (WPT) technologies. Especially, his major research topic is focused on chip-package-PCB co-design and co-simulation for signal integrity, power integrity, ground integrity, timing integrity, and radiated emission in 3D IC, TSV and Interposer.
He has authored and co-authored over 527 technical papers published at refereed journals and conference proceedings. Also, he has given more than 267 invited talks and tutorials at the academia and the related industries. He also was the conference chair of IEEE WPTC (Wireless Power Transfer Conference) 2014, held in Jeju Island, Korea. And he was the symposium chair of IEEE EDAPS Symposium 2008, and was the TPC chair of APEMC 2011He received Outstanding Academic Achievement Faculty Award of KAIST in 2006, KAIST Grand Research Award in 2008, National 100 Best Project Award in 2009, KAIST International Collaboration Award in 2010, KAIST Grand Research Award in 2014, and Teaching Award in 2015, respectively. He was appointed as an IEEE EMC society distinguished lecturer in a period from 2009-2011. He received Technology Achievement Award from IEEE Electromagnetic Society in 2010. He is IEEE fellow.
Dr. Chee Lip Gan
Professor, School of Material Science and Engineering, Nanyang Technological University
Dr Gan is a Professor at the School of Materials Science and Engineering, Nanyang Technological University. He is currently the Director of Temasek Laboratories@NTU and Executive Director of the Office of Research & Technology in Defence & Security. He is a Fellow of Renaissance Engineering Programme (REP), as well as a Fellow of NTU Teaching Excellence Academy. Dr Gan received his B.Eng (Electrical) from the National University of Singapore in 1999, and Ph.D in Advanced Materials for Micro- and Nano-Systems under the Singapore-MIT Alliance Program (SMA) in 2003. His research interests include the reliability study of advanced interconnect systems and advanced packaging technology for harsh environment electronics. in 2016. Dr Gan is a Senior Member of IEEE and board member of the International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), and past Chairman of IEEE Singapore Reliability/ED/EPS joint chapter.
Although lead-free tin-based solders is the dominant material currently used in microelectronics packaging, gold-based solders or silver nanoparticles pastes are also used in applications where high thermal conductivity between joints are required. In this study, we evaluate the application of copper nanoparticles paste as a die attach material. The copper nanoparticles have a size less than 20 nm which allows low temperature fusion, an organic passivation layer which prevents spontaneous particle fusion and growth at ambient temperatures, as well as avoiding oxidation before its usage. We studied the mechanical strength of Si chips bonded with the copper nanoparticles paste, and they demonstrate good reliability after thermal aging tests. We then applied the paste to bond commercial high power LED chips to ceramic substrate, which gives better electrical and optical properties than Au-Sn solders while maintaining the mechanical strength of the joint. We also developed copper nanoparticles ink that can be deposited on polymer substrates. We demonstrate that the electrical and mechanical properties of the sintered film on polymer substrates can be improved with the addition of nanowires to the ink.