Dr. Saikumar Jayaraman
In recent years there has been an increased interest in advanced packaging technologies for heterogeneous on-package integration as a way of providing increased functionality in compact form factors. This talk will start with a discussion on the motivations behind the market driven interest in heterogeneous integration. This will be followed by a review of the current state of the art packaging technologies that enable, highly power efficient, bandwidth on-package links. The focus will be on comparing key features of cutting edge 2.5D packaging technologies using on-package memory integration as a representative example. This is followed by a detailed review of Intel’s EMIB technology and its current product instantiations. The talk concludes with a description of the challenges and opportunities in the continued evolution of advanced packaging technologies.
Saikumar Jayaraman is a Senior Engineering TD Manager and Technologist who currently leads a strategic group involved in the advanced on-package integration of Memory, Sockets and External silicon. Sai has also has successfully led underfill materials, Tool and process development, Laser Mark process development, Die Prep material, Process, and Tool development, wafer level bumping, and 450mm assembly enablement in Intel’s Assembly and Test Technology Development Group. He has a highly distinguished record with more than 125 granted patents and over 50 publications. His research interest includes synthesis and development of novel materials and process for microelectronics applications. Sai received his Master’s degree in Polymer Chemistry from Madras University (Madras, India) in 1988 and a second Masters degree in Chemistry from Wright State University, Dayton, Ohio in 199, focusing on physical characterization of Maleimides composites. He finished his PhD in Chemistry, with focus on high temperature polymers and nano foams from Virginia Polytechnic Institute and State University, Blacksburg, Virginia in 1995. After his PhD, Sai joined BF Goodrich, working on development of novel cyclic olefin polymeric materials for electronic and optical applications. This work has led to the development of new 193nm lithographic materials and novel dielectric and optical wave-guide materials. Sai joined Intel in 2000 in the Assembly and Test Technology Division of Intel Corporation.
Dr. Mitsumasa Koyanagi
Professor, Tohoku University, Japan
Novel 3D/2.5D heterogeneous integration technologies using self-assembly have been developed to achieve high-throughput and high-precision multichip-to-wafer stacking. Many known good dies (KGDs) are simultaneously self-assembled on a carrier wafer with a high alignment accuracy making use of liquid surface tension. The self-assembled dies on the carrier are simultaneously transferred to another wafer or interposer wafer by electrostatically de-bonding the carrier wafer after Cu nano-pillar hybrid bonding of self-assembled dies. These liquid surface tension technologies have been also applied for massively parallel self-assembling of known good dies (KGDs) on large-area substrates such as glass panels and rigid/flexible organic substrates. Three kinds of large-area 3D/2.5D hetero integration technologies, face-down self-assembly/direct stacking with via-middle TSVs, face-down self-assembly/direct stacking with via-last TSVs, and face-up self-assembly/transfer stacking with via-last TSVs, are demonstrated.
In addition, a new TSV formation methodology based on advanced Directed Self-Assembly (DSA) with nanocomposites consisting of nano metal particles and block-co-polymers is proposed. Cylindrical nano-ordered structures with metal which act as nano-TSV are formed in Si deep holes through phase separation of polystyrene-block-poly methyl methacrylate polymers (PS-b-PMMA). These new self-assembly technologies have been applied to develop new heterogeneous 3D/2.5D LSI and system module for IoT and AI including neuro LSI.
He received the Ph.D. degree in electronic engineering from Tohoku University in 1974. He joined the Central Research Laboratory, Hitachi Ltd. in 1974 where he worked on MOS memory device and process technology and invented a stacked capacitor DRAM memory cell. In 1985, he joined the Xerox Palo Alto Research Center, California where he worked on CMOS devices, poly-Si TFT and the design of analog/digital LSIs. In 1988 he joined Hiroshima University where he worked on sub-0.1um device, poly-Si TFT, 3D integration, optical interconnection and parallel computer system. Since 1994, he has been a professor in Tohoku University where his research interests have been 3D integration, optical interconnection, nano-CMOS devices, memory devices, parallel computer system, brain-type computer, retinal prosthesis and neural prosthesis chips. He established the 3D LSI fabrication facility for 12-inch wafers, GINTI (Global Integration Initiative) in 2013 and became a director. He was awarded the 2006 IEEE Jun-ichi Nishizawa Medal, the 1996 IEEE Cledo Brunetti Award, the National Medal with Purple Ribbon in Japan in 2011, and the 3DIC Pioneer Award in 2015. He is an IEEE Life fellow.
Dr. Yongki Min
Intel Corporation, Materials Technologist, USA
Multilayer Ceramic Capacitors (MLCC) are one of most commonly used passive components in electronic packaging. The miniaturization and multiple functionality of the electronic device have driven the need for smaller capacitors with high capacitance value. To increase the capacitance density, capacitor manufactures have reduced the thickness of capacitor dielectric layers, and this has enabled the production of cutting edge small form factor capacitors. However, thinning the dielectric layer can negatively impact the capacitor’s rated voltage, DC bias characteristic, and usable life. In addition to the reduction of dielectric layer thickness, capacitor manufactures have also started to increase MLCC case size abnormally to meet the accelerated market demand of higher capacitance density. In recent years, the capacitor performance impact from the dielectric layers thickness reduction has become more severe, and resulted in a slowdown in the high capacitance density MLCC development cycle. Therefore, without the capacitor technology breakthrough, it will be difficult to keep the current pace of electronic devices revolution.
Yongki Min received his Bachelor’s and Master’s degrees in Metallurgical Engineering from Yonsei University, Korea. He worked at Daewoo Electronics in Korea for 5 years, focusing on MEMS display technology. In 2003, he received a Ph.D. in Materials Science and Engineering from the Massachusetts Institute of Technology. He started his career in Assembly & Test Technology Development (ATTD) at Intel Corporation, Chandler, AZ. Currently, he is the Materials Technologist responsible for the passive components portfolio of Intel product packages, and the primary role is to drive components technology innovation and lead passive components materials & suppliers’ PF/Dev/Cert & Ramp. He has 46 US patents in the field of MEMS display, passive components and package technologies.
Dr. Gyungock Kim
Electronics & Telecommunications Research Institute (ETRI)
Silicon photonics technology, providing CMOS-compatible platform for optical interconnects, is regarded as a future technology for computing and communication systems. In this talk, we present ETRI’s major works on silicon photonic devices and photonic integrated circuits (PICs) based on SOI platform or bulk-silicon platform for optical interconnects, and their practical applications. First, we overview Si-PICs for inter-chip/intra-chip optical interconnects, where Si optical modulators and Ge/Si PDs were monolithically integrated on SOI, operating up to 40~50 Gbps, and a new scheme of small-size vertically-dipped depletion-junction (VDJ) MZ modulator operating 50 Gb/s. We also present all-silicon photonic receiver and transmitter, operating up to 36 Gb/s, where Si photonic devices and CMOS ICs were hybrid-integrated. We introduce a bulk-Si photonic platform for practical implementation of chip-level optical interconnects (OIs), and the performance level. We have proposed a new integration scheme of single-chip photonic TRx as a bulk-Si platform for viable chip-level optical I/Os, based on a monolithic-integrated vertical photonic I/O device set including light source. We demonstrated a prototype of single-chip photonic TRx, realizing low-power chip-level OIs between chips. It can be also advantageous for 3D OIs in stacked ICs. Currently, ETRI is conducting a research on bulk-Si photonic platform for 2D/3D OIs. Success of this research can give a significant impact on practical electronic-photonic integrations. We also present high performance vertical-illumination-type Ge/Si PDs and APDs on bulk-Si, ready for practical applications.
Gyungock Kim received the B.S. and M.S. degrees in physics education, and physics from Seoul National University, Seoul, Korea, in 1979 and 1981, respectively, and the Ph. D. degree in physics from University of Notre Dame, Notre Dame, IN, USA in 1988. From 1988 to 1991, she was a research associate in Synchrotron resource of HHMI, and a member of participating research team of NSLS in BNL, Upton, NY, USA. She also held the part-time postdoctoral position in Columbia University, New York, NY, USA, from 1990 to 1991. She joined Electronics & Telecommunications Research Institute (ETRI), Daejeon, Korea in 1992, where she is currently a principal member of research staff. From 2004 to 2005, she was the director of the Optical devices research department. Since 2006, she is in charge of the silicon photonics research project of ETRI. From 2007 to 2017, she was a professor in the department of Advance device engineering, University of Science and Technology (UST), Daejeon, Korea. She has mainly investigated semiconductor quantum electronic/optoelectronic devices, ultra-high speed optoelectronic devices, and silicon photonic devices and integrated circuits.